1. Technical Field
The present invention relates generally to memory circuits, and more particularly to a memory array test circuit having bitlines cascaded with drive devices and associated methods for evaluating memory cell performance.
2. Description of the Related Art
Memory speed and other performance factors are critical limitations in today's processing systems and are predicted to become even more of a critical limitation as technologies move forward. In particular, static random access memories (SRAMS) and memory cells are used in processor caches, registers and in some designs external to the system processors for fast access to data and program instructions.
With processor cycle frequencies reaching well above 4 Ghz, development of SRAM cells that can store and provide access to stored values within that period has become necessary. However, measuring operating performance of memory cells in the presence of actual loading conditions presents a challenge.
Memory cell transition times, along with many other digital circuits have been evaluated using ring oscillator circuits wherein a large number of cells are cascaded with feedback of the output arranged in a ring configuration. The frequency at which the ring oscillator operates indicates the transition time performance, which provides some measure of ultimate operating frequency and access times. Typically, the cell design is then changed in subsequent design iterations having parameters adjusted in response to the results of the ring oscillator test.
However, present ring oscillator circuits and other delay-oriented circuits for performing delay tests typically either are not applied on production dies or they do not test the memory cells under loading conditions identical to placement of the cells within an actual memory array. Since, memory arrays are organized in rows and columns, bitlines common to each cell in a column provide loading from the bitline wire (metal) paths as well as the other cells in the column. In order to determine the performance of a memory cell design and process, the bitline loading must be considered and measured.
It is therefore desirable to provide a circuit and method for evaluating memory cell delay performance under operating conditions that are as close to actual bit-line loading conditions as possible. It is further desirable to provide such a test circuit that can be selectively enabled on production dies so that on-going evaluation during the production life span of a memory design can be performed.